DMB DSB ISB

https://blog.naver.com/signal97/221044676429 https://tot0rokr.github.io/arm64/barrier/pipeline-barrier-isb-dmb-dsb-ordering/

https://developer.arm.com/documentation/dui0489/c/arm-and-thumb-instructions/miscellaneous-instructions/dmb—dsb—and-isb

DMB (Data Memory Barrier) §

https://developer.arm.com/documentation/ddi0602/2023-12/Base-Instructions/DMB—Data-Memory-Barrier-?lang=en Data Memory Barrier is a memory barrier that ensures the ordering of observations of memory accesses, see Data Memory Barrier.

DSB (Data Synchronization Barrier) §

https://developer.arm.com/documentation/ddi0602/2023-12/Base-Instructions/DSB—Data-Synchronization-Barrier-?lang=en Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier.

ISB (Instruction Synchronization Barrier) §

Instruction Synchronization Barrier flushes the pipeline in the PE and is a context synchronization event. For more information, see Instruction Synchronization Barrier (ISB). https://developer.arm.com/documentation/ddi0602/2023-12/Base-Instructions/ISB—Instruction-Synchronization-Barrier-?lang=en