DAIF: Interrupt Mask Bits
Allows access to the interrupt mask bits. https://developer.arm.com/documentation/ddi0601/2023-12/AArch64-Registers/DAIF—Interrupt-Mask-Bits
D bit[9]
Debug Whether to mask Watchpoint, Breakpoint, Software Step exceptions targeted at the current Exception Level When the target Exception level of debug exception is higher than the current Exception level, the exception will not be masked by D Defaults to 1 on warm reset
| D | Meaning |
|---|---|
| 0 | not masked |
| 1 | masked |
A bit[8]
SError(SystemError) Exception mask bit Defaults to 1 on warm reset
| A | Meaning |
|---|---|
| 0 | Exception not masked |
| 1 | Exception masked |
I bit[7]
IRQ mask bit Defaults to 1 on warm reset
| I | Meaning |
|---|---|
| 0 | Exception not masked |
| 1 | Exception masked |
F bit[6]
FIQ mask bit Defaults to 1 on warm reset
| F | Meaning |
|---|---|
| 0 | Exception not masked |
| 1 | Exception masked |