Interrupt Registers
UARTICR: Interrupt Clear Register
| Bits | Name | Function |
|---|---|---|
| 15:11 | Reserved | Reserved, read as zero, do not modify. |
| 10 | OEIC | Overrun error interrupt clear. Clears the UARTOEINTR interrupt. |
| 9 | BEIC | Break error interrupt clear. Clears the UARTBEINTR interrupt. |
| 8 | PEIC | Parity error interrupt clear. Clears the UARTPEINTR interrupt. |
| 7 | FEIC | Framing error interrupt clear. Clears the UARTFEINTR interrupt. |
| 6 | RTIC | Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. |
| 5 | TXIC | Transmit interrupt clear. Clears the UARTTXINTR interrupt. |
| 4 | RXIC | Receive interrupt clear. Clears the UARTRXINTR interrupt. |
| 3 | DSRMIC | nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. |
| 2 | DCDMIC | nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. |
| 1 | CTSMIC | nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. |
| 0 | RIMIC | nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. |
UARTIFLS: Interrupt FIFO Level Select Register
| Bits | Name | Function |
|---|---|---|
| 15:6 | - | Reserved, do not modify, read as zero. |
| 5:3 | RXIFLSEL | Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes ≥ 1/8 full b001 = Receive FIFO becomes ≥ 1/4 full b010 = Receive FIFO becomes ≥ 1/2 full b011 = Receive FIFO becomes ≥ 3/4 full b100 = Receive FIFO becomes ≥ 7/8 full b101-b111 = reserved. |
| 2:0 | TXIFLSEL | Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes ≤ 1/8 full b001 = Transmit FIFO becomes ≤ 1/4 full b010 = Transmit FIFO becomes ≤ 1/2 full b011 = Transmit FIFO becomes ≤ 3/4 full b100 = Transmit FIFO becomes ≤ 7/8 full b101-b111 = reserved. |
UARTIMSC: Interrupt Mask.Set.Clear Register
| Bits | Name | Function |
|---|---|---|
| 15:11 | - | Reserved, read as zero, do not modify. |
| 10 | OEIM | Overrun error interrupt mask. A read returns the current mask for the UARTOEINTRinterrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. |
| 9 | BEIM | Break error interrupt mask. A read returns the current mask for the UARTBEINTRinterrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. |
| 8 | PEIM | Parity error interrupt mask. A read returns the current mask for the UARTPEINTRinterrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. |
| 7 | FEIM | Framing error interrupt mask. A read returns the current mask for the UARTFEINTRinterrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. |
| 6 | RTIM | Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTRinterrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. |
| 5 | TXIM | Transmit interrupt mask. A read returns the current mask for the UARTTXINTRinterrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. |
| 4 | RXIM | Receive interrupt mask. A read returns the current mask for the UARTRXINTRinterrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. |
| 3 | DSRMIM | nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. |
| 2 | DCDMIM | nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. |
| 1 | CTSMIM | nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. |
| 0 | RIMIM | nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. |
UARTMIS: Masked Interrupt Status Register
| Bits | Name | Function |
|---|---|---|
| 15:11 | - | Reserved, read as zero, do not modify |
| 10 | OEMIS | Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. |
| 9 | BEMIS | Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. |
| 8 | PEMIS | Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. |
| 7 | FEMIS | Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. |
| 6 | RTMIS | Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. |
| 5 | TXMIS | Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. |
| 4 | RXMIS | Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. |
| 3 | DSRMMIS | nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. |
| 2 | DCDMMIS | nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. |
| 1 | CTSMMIS | nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. |
| 0 | RIMMIS | nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. |