Offset | Name | Type | Reset | Width | Description |
---|
0x000 | UARTDR | RW | 0x--- | 12/8 | Data Register, UARTDR |
0x004 | UARTRSR/ UARTECR | RW | 0x0 | 4/0 | Receive Status Register / Error Clear Register, UARTRSR/UARTECR |
0x008-0x014 | - | - | - | - | Reserved |
0x018 | UARTFR | RO | 0b-10010--- | 9 | Flag Register, UARTFR |
0x01C | - | - | - | - | Reserved |
0x020 | UARTILPR | RW | 0x00 | 8 | IrDA Low-Power Counter Register, UARTILPR |
0x024 | UARTIBRD | RW | 0x0000 | 16 | Integer Baud Rate Register, UARTIBRD |
0x028 | UARTFBRD | RW | 0x00 | 6 | Fractional Baud Rate Register, UARTFBRD |
0x02C | UARTLCR_H | RW | 0x00 | 8 | Line Control Register, UARTLCR_H |
0x030 | UARTCR | RW | 0x0300 | 16 | Control Register, UARTCR |
0x034 | UARTIFLS | RW | 0x12 | 6 | Interrupt FIFO Level Select Register, UARTIFLS |
0x038 | UARTIMSC | RW | 0x000 | 11 | Interrupt Mask Set/Clear Register, UARTIMSC |
0x03C | UARTRIS | RO | 0x00- | 11 | Raw Interrupt Status Register, UARTRIS |
0x040 | UARTMIS | RO | 0x00- | 11 | Masked Interrupt Status Register, UARTMIS |
0x044 | UARTICR | WO | - | 11 | Interrupt Clear Register, UARTICR |
0x048 | UARTDMACR | RW | 0x00 | 3 | DMA Control Register, UARTDMACR |
0x04C-0x07C | - | - | - | - | Reserved |
0x080-0x08C | - | - | - | - | Reserved for test purposes |
0x090-0xFCC | - | - | - | - | Reserved |
0xFD0-0xFDC | - | - | - | - | Reserved for future ID expansion |
0xFE0 | UARTPeriphID0 | RO | 0x11 | 8 | UARTPeriphID0 Register |
0xFE4 | UARTPeriphID1 | RO | 0x10 | 8 | UARTPeriphID1 Register |
0xFE8 | UARTPeriphID2 | RO | 0x_4[1] | 8 | UARTPeriphID2 Register |
0xFEC | UARTPeriphID3 | RO | 0x00 | 8 | UARTPeriphID3 Register |
0xFF0 | UARTPCellID0 | RO | 0x0D | 8 | UARTPCellID0 Register |
0xFF4 | UARTPCellID1 | RO | 0xF0 | 8 | UARTPCellID1 Register |
0xFF8 | UARTPCellID2 | RO | 0x05 | 8 | UARTPCellID2 Register |
0xFFC | UARTPCellID3 | RO | 0xB1 | 8 | UARTPCellID3 Register |
Reference §
https://krinkinmu.github.io/2020/11/29/PL011.html
2 items under this folder.