12_UART

UART §

• Serial Communication Protocol & Hardware..
• UART로 키보드 입력 받음

PL011 Register Summary §

PL011 UART

• Documentation: https://developer.arm.com/documentation/ddi0183/g?lang=en
• PDF: https://documentation-service.arm.com/static/5e8e36c2fd977155116a90b5?token=
• Reference: https://krinkinmu.github.io/2020/11/29/PL011.html

Offset	Name	Type	Reset	Width	Description
0x000	UARTDR	RW	0x---	12/8	Data Register, UARTDR
0x004	UARTRSR/ UARTECR	RW	0x0	4/0	Receive Status Register / Error Clear Register, UARTRSR/UARTECR
0x008-0x014	-	-	-	-	Reserved
0x018	UARTFR	RO	0b-10010---	9	Flag Register, UARTFR
0x01C	-	-	-	-	Reserved
0x020	UARTILPR	RW	0x00	8	IrDA Low-Power Counter Register, UARTILPR
0x024	UARTIBRD	RW	0x0000	16	Integer Baud Rate Register, UARTIBRD
0x028	UARTFBRD	RW	0x00	6	Fractional Baud Rate Register, UARTFBRD
0x02C	UARTLCR_H	RW	0x00	8	Line Control Register, UARTLCR_H
0x030	UARTCR	RW	0x0300	16	Control Register, UARTCR
0x034	UARTIFLS	RW	0x12	6	Interrupt FIFO Level Select Register, UARTIFLS
0x038	UARTIMSC	RW	0x000	11	Interrupt Mask Set/Clear Register, UARTIMSC
0x03C	UARTRIS	RO	0x00-	11	Raw Interrupt Status Register, UARTRIS
0x040	UARTMIS	RO	0x00-	11	Masked Interrupt Status Register, UARTMIS
0x044	UARTICR	WO	-	11	Interrupt Clear Register, UARTICR
0x048	UARTDMACR	RW	0x00	3	DMA Control Register, UARTDMACR
0x04C-0x07C	-	-	-	-	Reserved
0x080-0x08C	-	-	-	-	Reserved for test purposes
0x090-0xFCC	-	-	-	-	Reserved
0xFD0-0xFDC	-	-	-	-	Reserved for future ID expansion
0xFE0	UARTPeriphID0	RO	0x11	8	UARTPeriphID0 Register
0xFE4	UARTPeriphID1	RO	0x10	8	UARTPeriphID1 Register
0xFE8	UARTPeriphID2	RO	0x_4[1]	8	UARTPeriphID2 Register
0xFEC	UARTPeriphID3	RO	0x00	8	UARTPeriphID3 Register
0xFF0	UARTPCellID0	RO	0x0D	8	UARTPCellID0 Register
0xFF4	UARTPCellID1	RO	0xF0	8	UARTPCellID1 Register
0xFF8	UARTPCellID2	RO	0x05	8	UARTPCellID2 Register
0xFFC	UARTPCellID3	RO	0xB1	8	UARTPCellID3 Register

Reference §

https://krinkinmu.github.io/2020/11/29/PL011.html

Link to original

Registers §

REGISTERS

Interrupt Registers §

Interrupts

Interrupt Registers §

UARTICR: Interrupt Clear Register §

Bits	Name	Function
15:11	Reserved	Reserved, read as zero, do not modify.
10	OEIC	Overrun error interrupt clear. Clears the UARTOEINTR interrupt.
9	BEIC	Break error interrupt clear. Clears the UARTBEINTR interrupt.
8	PEIC	Parity error interrupt clear. Clears the UARTPEINTR interrupt.
7	FEIC	Framing error interrupt clear. Clears the UARTFEINTR interrupt.
6	RTIC	Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.
5	TXIC	Transmit interrupt clear. Clears the UARTTXINTR interrupt.
4	RXIC	Receive interrupt clear. Clears the UARTRXINTR interrupt.
3	DSRMIC	nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.
2	DCDMIC	nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.
1	CTSMIC	nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.
0	RIMIC	nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.

UARTIFLS: Interrupt FIFO Level Select Register §

Bits	Name	Function
15:6	-	Reserved, do not modify, read as zero.
5:3	RXIFLSEL	Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes ≥ 1/8 full b001 = Receive FIFO becomes ≥ 1/4 full b010 = Receive FIFO becomes ≥ 1/2 full b011 = Receive FIFO becomes ≥ 3/4 full b100 = Receive FIFO becomes ≥ 7/8 full b101-b111 = reserved.
2:0	TXIFLSEL	Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes ≤ 1/8 full b001 = Transmit FIFO becomes ≤ 1/4 full b010 = Transmit FIFO becomes ≤ 1/2 full b011 = Transmit FIFO becomes ≤ 3/4 full b100 = Transmit FIFO becomes ≤ 7/8 full b101-b111 = reserved.

UARTIMSC: Interrupt Mask.Set.Clear Register §

Bits	Name	Function
15:11	-	Reserved, read as zero, do not modify.
10	OEIM	Overrun error interrupt mask. A read returns the current mask for the UARTOEINTRinterrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.
9	BEIM	Break error interrupt mask. A read returns the current mask for the UARTBEINTRinterrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.
8	PEIM	Parity error interrupt mask. A read returns the current mask for the UARTPEINTRinterrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.
7	FEIM	Framing error interrupt mask. A read returns the current mask for the UARTFEINTRinterrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.
6	RTIM	Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTRinterrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.
5	TXIM	Transmit interrupt mask. A read returns the current mask for the UARTTXINTRinterrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.
4	RXIM	Receive interrupt mask. A read returns the current mask for the UARTRXINTRinterrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.
3	DSRMIM	nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.
2	DCDMIM	nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.
1	CTSMIM	nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.
0	RIMIM	nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.

UARTMIS: Masked Interrupt Status Register §

Bits	Name	Function
15:11	-	Reserved, read as zero, do not modify
10	OEMIS	Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.
9	BEMIS	Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.
8	PEMIS	Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.
7	FEMIS	Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.
6	RTMIS	Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.
5	TXMIS	Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.
4	RXMIS	Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.
3	DSRMMIS	nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.
2	DCDMMIS	nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.
1	CTSMMIS	nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.
0	RIMMIS	nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.

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Implementation §

Initialization §

fn init(&mut self) {
	// Turn Off UART Temporarily
	self.registers.CR.set(0); 
	// Clear all interrupts
	self.registers.ICR.write(ICR::ALL::CLEAR); 
	// Set Baud Rate
	self.registers.IBRD.write(IBRD::BAUD_DIVINT.val(3));
	self.registers.FBRD.write(FBRD::BAUD_DIVINT.val(3));
	// Set DataFrame as 8bit + FIFO mode
	self.registers.LCR_H.write(LCR_H::WLEN::EightBit + LCR_H::FEN::FifosEnabled);
	self.registers.IFLS.write(IFLS::RXIFLSEL::OneEights);
	// Turn On Interrupt
	self.registers.IMSC.write(IMSC::RXIM::Enabled + IMSC::RTIM::Enabled);
	// Turn On UART
	self.registers.CR.write(CR::UARTEN::Enabled + CR::TXE::Enable + CR::RXE::Enabled);
}

Write Char to Console §

fn _write_char(&mut self, c: char) {
	self._flush();
	self.registers.DR.set(c as u32);
}

Read Char from Keyboard §

fn _read_char(&mut self, nonblocking: bool) {
	if nonblocking && self.registers.FR.matches_all(FR::RXFD::SET) {
		return None;
	}
	while self.registers.FR.matches_all(FR::RXFE::SET) {
		asm::nop();
	}
	let mut c = self.registers.DR.get() as u8 as char;
	if c == '\r' {
		c = '\n';
	}
	Some(c)
}

Flush §

fn _flush(&self) {
	while self.registers.FR.matches_all(FR::BUSY::SET) {
		asm::nop();
	}
}