CPSR: Current Program Status Register
https://developer.arm.com/documentation/ddi0601/2023-12/AArch32-Registers/CPSR—Current-Program-Status-Register?lang=en https://developer.arm.com/documentation/dui0473/m/overview-of-the-arm-architecture/current-program-status-register
- APSR flags
- Processor Mode
- Interrupt Disable Flags
- The Instruction set state (ARM, Thumb, ThumbEE or Jazelle)
- The endianness state (ARMv4tT and later)
- The execution state bits for the IT block (ARMv6T2 and later)
Fields
| 31 | 30 | 29 | 28 | 27 | 26~24 | 23 | 22 | 21 | 20 | 19~16 | 15~10 | 9 | 8 | 7 | 6 | 5 | 4 | 3~0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| N | Z | C | V | Q | RES0 | SSBS | PAN | DIT | RES0 | GE | RES0 | E | A | I | F | RES0 | RES1 | M |
E bit[9]
- Endianness State bit | E | Meaning | | --- | ----------------------- | | 0b0 | Little-Endian Operation | | 0b1 | Big-Endian Operation |
A bit[8]
SError(SystemError) Exception mask bit
| A | Meaning |
|---|---|
| 0 | Exception not masked |
| 1 | Exception masked |
I bit[7]
IRQ mask bit
| I | Meaning |
|---|---|
| 0 | Exception not masked |
| 1 | Exception masked |
F bit[6]
FIQ mask bit
| F | Meaning |
|---|---|
| 0 | Exception not masked |
| 1 | Exception masked |
M bit[3:0]
- Current PE Mode
| M | Meaning |
|---|---|
| 0b0000 | User |
| 0b0001 | FIQ |
| 0b0010 | IRQ |
| 0b0011 | Supervisor |
| 0b0110 | Monitor |
| 0b01111 | Abort |
| 0b1010 | Hyp. |
| 0b1011 | Undefined |
| 0b1111 | System |